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september 2003 this document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. tm tm tm spansion flash memory data sheet tm
ds05-20888-6e fujitsu semiconductor data sheet flash memory cmos 8 m (1 m 8/512 k 16) bit MBM29LV800TE 60/70/90 /mbm29lv800be 60/70/90 n description the MBM29LV800TE/be are a 8 m-bit, 3.0 v-only flash memory organized as 1 m bytes of 8 bits each or 512 kwords of 16 bits each. the MBM29LV800TE/be are offered in a 48-pin tsop (1) , 48-pin csop and 48- ball fbga package. these devices are designed to be programmed in a system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the devices can also be reprogrammed in standard eprom programmers. (continued) n product line up n packages part no. MBM29LV800TE/be ordering part no. v cc = 3.3 v 60 ?? v cc = 3.0 v ? 70 90 max address access time (ns) 60 70 90 max ce access time (ns) 60 70 90 max oe access time (ns) 30 30 35 48-pin plastic tsop (1) 48-pin plastic csop 48-ball plastic fbga (fpt-48p-m19) (lcc-48p-m03) (bga-48p-m20) + 0.3 v - 0.3 v + 0.6 v - 0.3 v
MBM29LV800TE/be 60/70/90 2 (continued) the standard MBM29LV800TE/be offer access times 60 ns, 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait state. to eliminate bus contention, the devices have separate chip enable (ce ) , write enable (we ) , and output enable (oe ) controls. the MBM29LV800TE/be are pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the devices is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the MBM29LV800TE/be are programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the devices automatically time the erase pulse widths and verify proper cell margin. a sector is typically erased and verified in 1.0 second. (if already completely preprogrammed.) the devices also feature a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the MBM29LV800TE/be are erased when shipped from the factory. the devices feature single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been completed, the devices internally resets to the read mode. the MBM29LV800TE/be also have hardware reset pins. when this pin is driven low, execution of any embedded program algorithm or embedded erase algorithm is terminated. the internal state machine is then reset to the read mode. the reset pin may be tied to the system reset circuitry. therefore, if a system reset occurs during the embedded program algorithm or embedded erase algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. these locations need re-writing after the reset. resetting the device enables the systems microprocessor to read the boot-up firmware from the flash memory. fujitsus flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the MBM29LV800TE/be memory electrically erase all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection.
MBM29LV800TE/be 60/70/90 3 n features ? 0.23 m m m m m process technology ? single 3.0 v read , program, and erase minimized system level power requirements ? compatible with jedec - standard commands use the same software commands as e 2 proms ? compatible with jedec - standard world - wide pinouts 48-pin tsop (1) (package suffix : tn normal bend type) 48-pin csop (package suffix : pcv) 48-ball fbga (package suffix : pbt) ? minimum 100,000 program / erase cycles ? high performance 70 ns maximum access time ? sector erase architecture one 8 kwords, two 4 kwords, one 16 kwords, and fifteen 32 kwords sectors in word mode one 16 kbytes, two 8 kbytes, one 32 kbytes, and fifteen 64 kbytes sectors in byte mode any combination of sectors can be concurrently erased, and also supports full chip erase. ? boot code sector architecture t = top sector b = bottom sector ? embedded erase tm * algorithm automatically pre-programs and erases the chip or any sector. ? embedded program tm * algorithm automatically writes and verifies data at specified address. ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready / busy output ( ry / by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, MBM29LV800TE/be automatically switch themselves to low power mode. ? low v cc write inhibit 2.5 v ? erase suspend / resume suspends the erase operation to allow a read data and/or program in another sector within the same device. ? sector protection hardware method disables any combination of sectors from program or erase operations. ? sector protection set function by extended sector protection command ? fast programming function by extended command ? temporary sector unprotection temporary sector unprotection via the reset pin * : embedde erase tm and embedded program tm are trademarks of advanced micro devices, inc.
MBM29LV800TE/be 60/70/90 4 n pin assignments (continued) 48 n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 47 35 46 45 44 43 42 41 40 39 38 37 36 34 33 32 31 30 29 28 27 26 25 a 3 a 2 a 4 a 1 a 6 a 7 a 18 a 17 ry/by n.c. we reset n.c. n.c. a 8 a 9 a 10 a 11 a 13 a 12 a 14 a 15 a 0 dq 1 dq 8 dq 0 oe v ss ce dq 2 dq 9 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 14 dq 6 dq 13 dq 7 byte v ss dq 15 /a -1 a 16 a 5 MBM29LV800TE/mbm29lv800be normal bend (marking side) tsop (1) (fpt-48p-m19)
MBM29LV800TE/be 60/70/90 5 (continued) (marking side) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a -1 v ss byte a 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 ry/by n.c. n.c. reset we n.c. n.c. a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 csop (top view) (lcc-48p-m03)
MBM29LV800TE/be 60/70/90 6 (continued) h1 a1 a2 a3 a4 a5 a6 f1 f2 f3 f4 b1 b2 b3 b4 b5 b6 f5 f6 g4 g5 c1 c2 c3 c4 h2 d5 e6 e5 e4 e3 e2 e1 h3 h4 g6 d6 d4 d3 d2 d1 g1 g2 g3 c6 c5 h5 h6 fbga (top view) marking side (bga-48p-m20) a1 a 3 a2 a 7 a3 ry/by a4 we a5 a 9 a6 a 13 b1 a 4 b2 a 17 b3 n.c. b4 reset b5 a 8 b6 a 12 c1 a 2 c2 a 6 c3 a 18 c4 n.c. c5 a 10 c6 a 14 d1 a 1 d2 a 5 d3 n.c. d4 n.c. d5 a 11 d6 a 15 e1 a 0 e2 dq 0 e3 dq 2 e4 dq 5 e5 dq 7 e6 a 16 f1 ce f2 dq 8 f3 dq 10 f4 dq 12 f5 dq 14 f6 byte g1 oe g2 dq 9 g3 dq 11 g4 v cc g5 dq 13 g6 dq 15 /a -1 h1 v ss h2 dq 1 h3 dq 3 h4 dq 4 h5 dq 6 h6 v ss
MBM29LV800TE/be 60/70/90 7 n pin description pin name function a 18 to a 0 , a -1 address inputs dq 15 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/temporary sector unprotection byte selects 8-bit or 16-bit mode n.c. no internal connection v ss device ground v cc device power supply
MBM29LV800TE/be 60/70/90 8 n block diagram n logic symbol a -1 v ss v cc we ce a 18 to a 0 oe dq 15 to dq 0 byte reset stb stb erase voltage generator state control command register program voltage generator input/output buffers data latch chip enable output enable logic low v cc detector timer for program/erase address latch y-decoder x-decoder y-gating cell matrix ry/by ry/by buffer 19 a 18 to a 0 we oe ce dq 15 to dq 0 16 or 8 byte reset a -1 ry/by
MBM29LV800TE/be 60/70/90 9 n device bus operation MBM29LV800TE/be user bus operations (byte = = = = v ih ) legend : l = v il , h = v ih , x = v il or v ih , = pulse input. see n dc characteristics for voltage levels. *1: manufacturer and device codes may also be accessed via a command register write sequence. see sector address tables (mbm29lv800be) in n flexible sector-erase architecture. *2: refer to sector protection. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = 3.0 v to 3.6 v (MBM29LV800TE/be 60) = 2.7 v to 3.6 v (MBM29LV800TE/be 70/90) *5: also used for the extended sector protection. operation ce oe we a 0 a 1 a 6 a 9 dq 15 to dq 0 reset auto-select manufacturer code * 1 llhlllv id code h auto-select device code * 1 llhhllv id code h read * 3 llha 0 a 1 a 6 a 9 d out h standby h x x xxxx high-z h output disable lhhxxxx high-z h write (program/erase) l h l a 0 a 1 a 6 a 9 d in h enable sector protection * 2, * 4 lv id lhlv id xh verify sector protection * 2, * 4 llhlhlv id code h temporary sector unprotection* 5 xxxxxxx x v id reset (hardware) /standby x x x xxxx high-z l
MBM29LV800TE/be 60/70/90 10 MBM29LV800TE/be user bus operations (byte = = = = v il ) legend : l = v il , h = v ih , x = v il or v ih , = pulse input. see n dc characteristics for voltage levels. *1: manufacturer and device codes may also be accessed via a command register write sequence. see sector address tables (mbm29lv800be) in n flexible sector-erase architecture. *2: refer to sector protection. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = 3.0 v to 3.6 v (MBM29LV800TE/be 60) = 2.7 v to 3.6 v (MBM29LV800TE/be 70/90) *5: also used for the extended sector protection. operation ce oe we dq 15 / a- 1 a 0 a 1 a 6 a 9 dq 7 to dq 0 reset auto-select manufacturer code * 1 llhllllv id code h auto-select device code * 1 llhlhllv id code h read * 3 llha -1 a 0 a 1 a 6 a 9 d out h standby h x x x xxxx high-z h output disable lhhxxxxx high-z h write (program/erase) l h l a -1 a 0 a 1 a 6 a 9 d in h enable sector protection * 2, * 4 lv id llhlv id xh verify sector protection * 2, * 4 llhllhlv id code h temporary sector unprotection * 5 xxxxxxxx x v id reset (hardware) /standby x x x x xxxx high-z l
MBM29LV800TE/be 60/70/90 11 MBM29LV800TE/be command definitions *1 : both of these reset commands are equivalent. *2 : this command is valid during fast mode. *3 : this command is valid while reset = v id (except during hiddenrom mode) . *4 : the data 00h is also acceptable. *5 : the fourth bus cycle is only for read. notes : address bits a 18 to a 11 = x = h or l for all address commands except or program address (pa) and sector address (sa) . bus operations are defined in MBM29LV800TE/be user bus operations (byte = v ih ) and MBM29LV800TE/be user bus operations (byte = v il ). ra = address of the memory location to be read. ia = autoselect read address that sets a 6 , a 1 , a 0 . pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset* 1 word 1xxxhf0h ?????????? byte read/reset* 1 word 3 555h aah 2aah 55h 555h f0h ra* 5 rd* 5 ???? byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h 555h 90h ia* 5 id* 5 ???? byte aaah 555h aaah program word 4 555h aah 2aah 55h 555h a0h pa pd ???? byte aaah 555h aaah chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h erase suspend 1 xxxh b0h ?????????? erase resume 1 xxxh 30h ?????????? set to fast mode word 3 555h aah 2aah 55h 555h 20h ?????? byte aaah 555h aaah fast program* 2 word 2 xxxh a0h pa pd ???????? byte xxxh reset from fast mode* 2 word 2 xxxh 90h xxxh * 4 f0h ???????? byte xxxh xxxh extended sector protection* 3 word 3 xxxh 60h spa 60h spa 40h spa* 5 sd* 5 ???? byte
MBM29LV800TE/be 60/70/90 12 rd = data read from location ra during read operation. id = device code/manufacture code for the address located by ia. pd = data to be programmed at location pa. data is latched on the rising edge of we . spa = sector address to be protected. set sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0) . sd = sector protection verify data. output 01h at protected sector addressed and output 00h at unprotected sector addresses. the system should generate the following address patterns : word mode : 555h or 2aah to addresses a 10 to a 0 byte mode : aaah or 555h to addresses a 10 to a- 1 both read/reset commands are functionally equivalent, resetting the device to the read mode. the command combinations not described in command definitions are illegal. MBM29LV800TE/be sector protection verify autoselect codes *1 : a -1 is for byte mode. at byte mode, dq 14 to dq 8 are high-z and dq 15 is a -1 , the lowest address. *2 : outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. expanded autoselect code table * : at byte mode, dq 14 to dq 8 are high-z and dq 15 is a -1 , the lowest address. (b) : byte mode (w) : word mode hi-z : high-z type a 18 to a 12 a 6 a 1 a 0 a -1 * 1 code (hex) manufactures code x v il v il v il v il 04h device code MBM29LV800TE byte xv il v il v ih v il dah word x 22dah mbm29lv800be byte xv il v il v ih v il 5bh word x 225bh sector protection sector addresses v il v ih v il v il 01h* 2 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h a -1 /00 0 0 0 0 0 0 00000100 device code mbm29 lv800te (b) dah a -1 hi-zhi-zhi-zhi-zhi-zhi-zhi-z11011010 (w) 22dah 0 0 1 0 0 0 1 0 11011010 mbm29 lv800be (b) 5bh a -1 hi-zhi-zhi-zhi-zhi-zhi-zhi-z01011011 (w) 225bh0 0 1 0 0 0 1 0 01011011 sector protection* 01h a -1 /00 0 0 0 0 0 0 00000001
MBM29LV800TE/be 60/70/90 13 n flexible sector-erase architecture sector address tables (MBM29LV800TE) sector address a 18 a 17 a 16 a 15 a 14 a 13 a 12 address range ( 8) address range ( 16) sa0 0 0 0 0 x x x 00000h to 0ffffh 00000h to 07fffh sa1 0 0 0 1 x x x 10000h to 1ffffh 08000h to 0ffffh sa2 0 0 1 0 x x x 20000h to 2ffffh 10000h to 17fffh sa3 0 0 1 1 x x x 30000h to 3ffffh 18000h to 1ffffh sa4 0 1 0 0 x x x 40000h to 4ffffh 20000h to 27fffh sa5 0 1 0 1 x x x 50000h to 5ffffh 28000h to 2ffffh sa6 0 1 1 0 x x x 60000h to 6ffffh 30000h to 37fffh sa7 0 1 1 1 x x x 70000h to 7ffffh 38000h to 3ffffh sa8 1 0 0 0 x x x 80000h to 8ffffh 40000h to 47fffh sa9 1 0 0 1 x x x 90000h to 9ffffh 48000h to 4ffffh sa10 1 0 1 0 x x x a0000h to affffh 50000h to 57fffh sa11 1 0 1 1 x x x b0000h to bffffh 58000h to 5ffffh sa12 1 1 0 0 x x x c0000h to cffffh 60000h to 67fffh sa13 1 1 0 1 x x x d0000h to dffffh 68000h to 6ffffh sa14 1 1 1 0 x x x e0000h to effffh 70000h to 77fffh sa15 1 1 1 1 0 x x f0000h to f7fffh 78000h to 7bfffh sa16 1 1 1 1 1 0 0 f8000h to f9fffh 7c000h to 7cfffh sa17 1 1 1 1 1 0 1 fa000h to fbfffh 7d000h to 7dfffh sa18 1 1 1 1 1 1 x fc000h to fffffh 7e000h to 7ffffh
MBM29LV800TE/be 60/70/90 14 sector address tables (mbm29lv800be) sector address a 18 a 17 a 16 a 15 a 14 a 13 a 12 address range ( 8) address range ( 16) sa0 0 0 0 0 0 0 x 00000h to 03fffh 00000h to 01fffh sa1 0 0 0 0 0 1 0 04000h to 05fffh 02000h to 02fffh sa2 0 0 0 0 0 1 1 06000h to 07fffh 03000h to 03fffh sa3 0 0 0 0 1 x x 08000h to 0ffffh 04000h to 07fffh sa4 0 0 0 1 x x x 10000h to 1ffffh 08000h to 0ffffh sa5 0 0 1 0 x x x 20000h to 2ffffh 10000h to 17fffh sa6 0 0 1 1 x x x 30000h to 3ffffh 18000h to 1ffffh sa7 0 1 0 0 x x x 40000h to 4ffffh 20000h to 27fffh sa8 0 1 0 1 x x x 50000h to 5ffffh 28000h to 2ffffh sa9 0 1 1 0 x x x 60000h to 6ffffh 30000h to 37fffh sa10 0 1 1 1 x x x 70000h to 7ffffh 38000h to 3ffffh sa11 1 0 0 0 x x x 80000h to 8ffffh 40000h to 47fffh sa12 1 0 0 1 x x x 90000h to 9ffffh 48000h to 4ffffh sa13 1 0 1 0 x x x a0000h to affffh 50000h to 57fffh sa14 1 0 1 1 x x x b0000h to bffffh 58000h to 5ffffh sa15 1 1 0 0 x x x c0000h to cffffh 60000h to 67fffh sa16 1 1 0 1 x x x d0000h to dffffh 68000h to 6ffffh sa17 1 1 1 0 x x x e0000h to effffh 70000h to 77fffh sa18 1 1 1 1 x x x f0000h to fffffh 78000h to 7ffffh
MBM29LV800TE/be 60/70/90 15 ? one 16 kbytes, two 8 kbytes, one 32 kbytes, and fifteen 64 kbytes ? individual-sector, multiple-sector, or bulk-erase capability ? individual or multiple-sector protection is user definable. ( 8) fffffh fbfffh f9fffh f7fffh effffh dffffh cffffh bffffh affffh 9ffffh 8ffffh 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh 00000h ( 1 6) 7ffffh 7dfffh 7cfffh 7bfffh 77fffh 6ffffh 67fffh 5ffffh 57fffh 4ffffh 47fffh 3ffffh 37fffh 2ffffh 27fffh 1ffffh 17fffh 0ffffh 07fffh 00000h 16 kbyte 8 kbyte 8 kbyte 32 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte ( 8) fffffh effffh dffffh cffffh bffffh affffh 9ffffh 8ffffh 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh 07fffh 05fffh 03fffh 00000h ( 1 6) 7ffffh 77fffh 6ffffh 67fffh 5ffffh 57fffh 4ffffh 47fffh 3ffffh 37fffh 2ffffh 27fffh 1ffffh 17fffh 0ffffh 07fffh 03fffh 02fffh 01fffh 00000h 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 32 kbyte 8 kbyte 8 kbyte 16 kbyte MBM29LV800TE sector architecture mbm29lv800be sector architecture
MBM29LV800TE/be 60/70/90 16 n functional description read mode the MBM29LV800TE/be have two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable for at least t acc -t oe time) . when reading out data without changing addresses after power-up, it is necessary to input hardware reset or change ce pin from h or l standby mode there are two ways to implement the standby mode on the MBM29LV800TE/be devices, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition, the current consumed is less than 5 m a. the device can be read with standard access time (t ce ) from either of these standby modes. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l) . under this condition the current consumed is less than 5 m a. once the reset pin is taken high, the device requires t rh as wake up time for outputs to be valid for read access. in the standby mode, the outputs are in the high impedance state, independently of the oe input. automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of MBM29LV800TE/be data. this mode can be useful in the application such as handy terminal which requires low power consumption. to activate this mode, MBM29LV800TE/be automatically switches themselves to low power mode when MBM29LV800TE/be addresses remain stable during access time of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 1 m a (cmos level) . since the data are latched during this mode, the data are read-out continuously. if the addresses are changed, the mode is canceled automatically, and MBM29LV800TE/be read-out the data for changed addresses. output disable with the oe input at a logic high level (v ih ) , the output from the devices is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the devices. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , a 6 , and a -1 . (see MBM29LV800TE/be sector protection verify autoselect codes in device bus operation.) the manufacturer and device codes may also be read via the command register, for instances when the MBM29LV800TE/be are erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in MBM29LV800TE/be command definitions in device bus opera- tion. (refer to autoselect command section.)
MBM29LV800TE/be 60/70/90 17 word 0 (a 0 = v il ) represents the manufacturers code (fujitsu = 04h) and (a 0 = v ih ) represents the device identifier code (MBM29LV800TE = dah and mbm29lv800be = 5bh for 8 mode; MBM29LV800TE = 22dah and mbm29lv800be = 225bh for 16 mode) . these two bytes/words are given in MBM29LV800TE/be sector protection verify autoselect codes and expanded autoselect code table in device bus operation. all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see MBM29LV800TE/be sector protection verify autoselect codes and expanded autoselect code table in device bus operation.) write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector protection the MBM29LV800TE/be feature hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 18) . the sector protection feature is enabled using programming equipment at the users site. the devices are shipped with all sectors unprotected. alternatively, fujitsu may program and protect sectors in the factory prior to shiping the device. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v) , ce = v il , and a 6 = v il . the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. sector address tables (MBM29LV800TE) and sector address tables (mbm29lv800be) in flexible sector-erase architecture define the sector address for each of the nineteen (19) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see sector protection timing diagram in timing diagram and sector protection algo- rithm in flow chart for sector protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the devices will read 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires to apply to v il on byte mode. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) are the desired sector address will produce a logical 1 at dq 0 for a protected sector. see MBM29LV800TE/be sector protection verify autoselect codes and expanded autoselect code table in device bus operation for autoselect codes. temporary sector unprotection this feature allows temporary unprotection of previously protected sectors of the MBM29LV800TE/be devices in order to change data. the sector unprotection mode is activated by setting the reset pin to high voltage (v id ) . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the v id is taken away from the reset pin, all the previously protected sectors will be protected again. see temporary sector unprotection timing diagram in timing diagram and temporary sector unprotection algorithm in flow chart.
MBM29LV800TE/be 60/70/90 18 extended sector protection in addition to normal sector protection, the MBM29LV800TE/be have extended sector protection as extended function. this function enables to protect sector by forcing v id on reset pin and write a commnad sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector protection in this mode. the extended sector protect requires v id on reset pin. with this condition the operation is initiated by writing the set-up command (60h) into the command register. then the sector addresses pins (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set to be protected (recommend to set v il for the other addresses pins) , and write extended sector protect command (60h) . a sector is generally protected in 250 m s. to verify programming of the protection circuitry, the sector addresses pins (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set and write a command (40h) . following the command write, a logical 1 at device output dq 0 produces for protected sector in the read operation. if the output is logical 0, repeat to write extended sector protect command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih (refer to extended sector protection algorithm in n flow chart) . reset hardware reset the MBM29LV800TE/be devices may be reset by driving the reset pin to v il . the reset pin has pulse requirement and has to be kept low (v il ) for at least t rp in order to properly reset the internal state machine. any operation in the process of being executed is terminated and the internal state machine is reset to the read mode t ready after the reset pin goes low. furthermore once the reset pin goes high, the devices require an additional t rh before it will allow read access. when the reset pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if hardware reset occurs during program or erase operation, the data at that particular location is corrupted. note that the ry/by output signal should be ignored during the reset pulse. see reset , ry/by timing diagram in n timing diagram for the timing diagram. refer to temporary sector unprotection for additional functionality. if hardware reset occurs during embedded erase algorithm, the erasing sector (s) cannot be used.
MBM29LV800TE/be 60/70/90 19 n command definitions device operations are selected by writing specific address and data sequences into the command register. MBM29LV800TE/be command definitions in n device bus operation defines the valid register com- mand sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. furthermore both read/reset commands are functionally equivalent, resetting the device to the read mode. note that commands are always written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the devices remain enabled for reads until the command register contents are altered. the devices will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read character- istics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such manufacture and device codes must be accessible while the devices reside in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a high voltage. however multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. following the command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address xx01h for 16 (xx02h for 8) returns the device code (MBM29LV800TE = dah and mbm29lv 800be = 5bh for 8 mode; MBM29LV800TE = 22dah and mbm29lv800be = 225bh for 16 mode) . (see MBM29LV800TE/be sector protection verify autoselect codes and expanded autoselect code table in n device bus operation.) all manufacturer and device codes will exhibit odd parity with dq 7 defined as the parity bit. sector state (protection or unprotection) will be informed by address xx02h for 16 (xx04h for 8). scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. the programming verification should be performed margin mode on the protected sector. (see MBM29LV800TE/be user bus operations (byte = v ih ) and mbm29lv 800te/be user bus operations (byte = v il ) in n device bus operation.) to terminate the operation, it is necessary to write the read/reset command sequence into the register. to execute the autoselect command during the operation, writing read/reset command sequence must precede the autoselect command. byte/word programming the devices are programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (see hardware sequence flags.) therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed.
MBM29LV800TE/be 60/70/90 20 if hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. embedded program tm algorithm in n flow chart illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (preprogram function) . the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read the mode. chip erase time; sector erase time all sectors + chip program time (preprogramming) embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (data = 30h) is latched on the rising edge of we . after time-out of t tow from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations on MBM29LV800TE/be command definitions in n device bus operation. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than t tow otherwise that command will not be accepted and erasure will not start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re- enabled after the last sector erase command is written. a time-out of t tow from the rising edge of the last we will initiate the execution of the sector erase command (s) . if another falling edge of the we occurs within the t tow time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) once execution has begun resetting the devices will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 18) . sector erase does not require the user to program the devices prior to erase. the devices automatically program all memory locations in the sector (s) to be erased prior to electrical erase (preprogram function) . when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the t tow time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the devices return to the read mode. data polling must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector erase time + sector program time (preprogram- ming) ] number of sector erase
MBM29LV800TE/be 60/70/90 21 embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. writting the erase suspend command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command resumes the erase operation. the addresses are dont cares when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a maximum of t spd to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/ by output pin and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the devices default to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector will cause dq 2 to toggle while the device is in the erase-suspend-read mode (see the section on dq 2 ) . after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode is known as the erase-suspend-program mode. again, pro- gramming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the ry/by output pin, data polling of dq 7 , or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. extended command (1) fast mode MBM29LV800TE/be have fast mode function. this mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. in fast mode, do not write any command other than the fast program/fast mode reset command. the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register (refer to embedded programming algorithm for fast mode in n flow chart) . the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd) (refer to embedded programming algorithm for fast mode in n flow chart) .
MBM29LV800TE/be 60/70/90 22 write operation status hardware sequence flags *1 : performing successive read operations from any address will cause dq 6 to toggle. *2 : reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. notes : dq 1 and dq 0 are reserved pins for future use. dq 4 is fujitsu internal use only. dq 7 data polling the MBM29LV800TE/be devices feature data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read devices will produce a complement of data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read device will produce true data last written to dq 7 . during the embedded erase algorithm, an attempt to read device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read device will produce a 1 on dq 7 . the flowchart for data polling (dq 7 ) is shown in data polling algorithm in n flow chart. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse sequence. data polling must be performed at sector address of sectors being erased, not protected sectors. otherwise, the status may be invalid. once the embedded algorithm operation is close to completion, MBM29LV800TE/be data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that devices are driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if device has completed the embedded algorithm operation and dq 7 has a valid data, data outputs on dq 6 to dq 0 may be still invalid. the valid data on dq 7 to dq 0 will be read on the successive read attempts. the data polling feature is active only during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. see data polling during embedded algorithm operation timing diagram in n timing diagram for the data polling timing specifications and diagrams. status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle erase suspended mode erase suspend read (erase suspended sector) 1 1 0 0 toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle* 1 00 1* 2 exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
MBM29LV800TE/be 60/70/90 23 dq 6 toggle bit i the MBM29LV800TE/be also feature the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the devices will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during pro- gramming, the toggle bit i is valid after the rising edge of the fourth we pulses in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth we pulse in the six write pulses sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written is protected, the toggle bit will toggle for about 2 m s and then stop toggling with data unchanged. in erase, devices will erase all selected sectors except for ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 200 m s and then drop back into read mode, having data unchanged. either ce or oe toggling will cause dq 6 to toggle. in addition, an erase suspend/resume command will cause dq 6 to toggle. see taggle bit i during embedded algorithm operation timing diagram in n timing diagram for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . under these conditions, dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of devices under this condition. the ce circuit will partially power down device under these conditions (to approximately 2 ma) . the oe and we pins will control the output disable functions as described in MBM29LV800TE/be user bus operations (byte = v ih ) and MBM29LV800TE/be user bus operations (byte = v il ) in n device bus operation. the dq 5 failure condition may also appear if a user tries to program a non blank location without pre-erase. in this case, the devices lock out and never complete the embedded algorithm operation. hence, the system never read valid data on dq 7 bit and dq 6 never stop toggling. once devices have exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since devices were incorrectly used. if this occurs, reset device with command sequence. dq 3 sector erase timer after completion of the initial sector erase command sequence, sector erase time-out will begin. dq 3 will remain low until the time-out is completed. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun : if dq 3 is low (0) , the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see hardware sequence flags.
MBM29LV800TE/be 60/70/90 24 dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows : for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also hardware sequence flags and dq 2 vs. dq 6 in n timing diagram. furthermore, dq 2 can also be used to determine which sector is being erased. when device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. toggle bit status *1 : performing successive read operations from any address will cause dq 6 to toggle. *2 : reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. ry/by ready/busy MBM29LV800TE/be provide a ry/by open-drain output pin as a way to indicate to the host system that em- bedded algorithms are either in progress or has been completed. if output is low, devices are busy with either a program or erase operation. if output is high, devices are ready to accept any read/write or erase operation. if MBM29LV800TE/be are placed in an erase suspend mode, ry/by output will be high. during programming, ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, ry/by pin is driven low after the rising edge of the sixth we pulse. ry/by pin will indicate a busy condition during reset pulse. refer to ry/by timing diagram during program/erase operation timing diagram and reset , ry/by timing diagram in n timing diagram for a detailed timing diagram. ry/by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle erase-suspend read (erase-suspended sector) * 1 11toggle erase-suspend program dq 7 toggle * 1 1 * 2
MBM29LV800TE/be 60/70/90 25 byte/word configuration byte pin selects byte (8-bit) mode or word (16-bit) mode for MBM29LV800TE/be devices. when this pin is driven high, devices operate in word (16-bit) mode. data is read and programmed at dq 15 to dq 0 . when this pin is driven low, devices operates in byte (8-bit) mode. under this mode, the dq 15 /a- 1 pin becomes the lowest address bit, and dq 14 to dq 8 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. refer to timing diagram for word mode configuration, timing diagram for byte mode configuration and byte timing diagram for write operations in n timing diagram for the timing diagram. data protection MBM29LV800TE/be are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up, devices automatically reset internal state machine in read mode. also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. devices also incorporate several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than v lko (min) . if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition, the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above v lko (min) . if embedded erase algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used. write pulse glitch protection noise pulses of less than 3 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle, ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
MBM29LV800TE/be 60/70/90 26 n absolute maximum ratings *1 : voltage is defined on the basis of v ss = gnd = 0 v. *2 : minimum dc voltage on input or l/o pins is - 0.5 v. during voltage transitions, inputs or i/o pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc voltage on input or l/o pins is v cc + 0.5 v. during voltage transitions, inputs or i/o pins may overshoot to v cc + 2.0 v for periods of up to 20 ns. *3 : minimum dc input voltage on a 9 , oe , and reset pins is - 0.5 v. during voltage transitions, a 9 , oe , and reset pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in - v cc ) does not exceed + 9.0 v. maximum dc input voltage on a 9 , oe , and reset pins is + 13.0 v which may overshoot to + 14.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions * : voltage is defined on the basis of v ss = gnd = 0 v. note : operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg - 55 + 125 c ambient temperature with power applied t a - 40 + 85 c voltage with respect to ground all pins except a 9 , oe , reset * 1, * 2 v in , v out - 0.5 v cc + 0.5 v power supply voltage * 1 v cc - 0.5 + 5.5 v a 9 , oe , and reset * 1, * 3 v in - 0.5 + 13.0 v parameter symbol part no. value unit min typ max ambient temperature t a MBM29LV800TE/be 60 - 20 ?+ 70 c MBM29LV800TE/be 70/90 - 40 ?+ 85 c power supply voltage* v cc MBM29LV800TE/be 60 + 3.0 ?+ 3.6 v MBM29LV800TE/be 70/90 + 2.7 ?+ 3.6 v
MBM29LV800TE/be 60/70/90 27 n maximum overshoot/maximum undershoot + 0.6 v - 0.5 v 20 ns - 2.0 v 20 ns 20 ns maximum undershoot waveform v cc + 0.5 v + 2.0 v v cc + 2.0 v 20 ns 20 ns 20 ns maximum overshoot waveform 1 + 13.0 v v cc + 0.5 v + 14.0 v 20 ns 20 ns 20 ns maximum overshoot waveform 2 note : this wave form is applied for a 9 , oe , and reset .
MBM29LV800TE/be 60/70/90 28 n dc characteristics *1: i cc current listed includes both the dc operating current and the frequency dependent component (at 10 mhz) . *2: i cc is active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: (v id - v cc ) do not exceed 9 v. parameter symbol test conditions value unit min max input leakage current i li v in = v ss to v cc , v cc = v cc max - 1.0 + 1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max - 1.0 + 1.0 m a a 9 , oe , reset inputs leakage current i lit v cc = v cc max, a 9 , oe , reset = 12.5 v ? 35 m a v cc active current * 1 i cc1 ce = v il , oe = v ih , f = 10 mhz byte ? 22 ma word 25 ce = v il , oe = v ih , f = 5 mhz byte ? 12 ma word 15 v cc active current * 2 i cc2 ce = v il , oe = v ih ? 35 ma v cc current (standby) i cc3 v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v ? 5 m a v cc current (standby, reset) i cc4 v cc = v cc max, reset = v ss 0.3 v ? 5 m a v cc current (automatic sleep mode) * 3 i cc5 v cc = v cc max, ce = v ss 0.3 v, reset = v cc 0.3 v, v in = v cc 0.3 v or v ss 0.3 v ? 5 m a input low level v il ?- 0.5 0.6 v input high level v ih ? 2.0 v cc + 0.3 v voltage for autoselect and sector protection (a 9 , oe , reset ) * 4 v id ? 11.5 12.5 v output low voltage level v ol i ol = 4.0 ma, v cc = v cc min ? 0.45 v output high voltage level v oh1 i oh = - 2.0 ma, v cc = v cc min 2.4 ? v v oh2 i oh = - 100 m av cc - 0.4 ? v low v cc lock-out voltage v lko ? 2.3 2.5 v
MBM29LV800TE/be 60/70/90 29 n ac characteristics ? read only operations characteristics parameter symbols test setup value* unit 60 70 90 jedec standard min max min max min max read cycle time t avav t rc ? 60 ? 70 ? 90 ? ns address to output delay t avqv t acc ce = v il oe = v il ? 60 ? 70 ? 90 ns chip enable to output delay t elqv t ce oe = v il ? 60 ? 70 ? 90 ns output enable to output delay t glqv t oe ?? 30 ? 30 ? 35 ns chip enable to output high-z t ehqz t df ?? 25 ? 25 ? 30 ns output enable to output high-z t ghqz t df ?? 25 ? 25 ? 30 ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh ? 0 ? 0 ? 0 ? ns reset pin low to read mode ? t ready ?? 20 ? 20 ? 20 m s ce to byte switching low or high ? t elfl t elfh ?? 5 ? 5 ? 5ns * : test conditions : output load : 1 ttl gate and 30 pf (MBM29LV800TE60/be60, MBM29LV800TE70/be70) 1 ttl gate and 100 pf (MBM29LV800TE90/be90) input rise and fall times : 5 ns input pulse levels : 0.0 v or 3.0 v timing measurement reference level input : 1.5 v output : 1.5 v c l 3.3 v diode = 1n3064 or equivalent 2.7 k w device under test diode = 1n3064 or equivalent 6.2 k w test conditions note : c l = 30 pf including jig capacitance (MBM29LV800TE60/be60, MBM29LV800TE70/be70) c l = 100 pf including jig capacitance (MBM29LV800TE90/be90)
MBM29LV800TE/be 60/70/90 30 ? write / erase / program operations (continued) parameter symbol MBM29LV800TE/be unit 60 70 90 jedec standard min typ max min typ max min typ max write cycle time t avav t wc 60 ?? 70 ?? 90 ?? ns address setup time t avwl t as 0 ?? 0 ?? 0 ?? ns address hold time t wlax t ah 45 ?? 45 ?? 45 ?? ns data setup time t dvwh t ds 30 ?? 35 ?? 45 ?? ns data hold time t whdx t dh 0 ?? 0 ?? 0 ?? ns output enable setup time ? t oes 0 ?? 0 ?? 0 ?? ns output enable hold time read ? t oeh 0 ?? 0 ?? 0 ?? ns toggle and data polling 10 ?? 10 ?? 10 ?? ns read recover time before write t ghwl t ghwl 0 ?? 0 ?? 0 ?? ns read recover time before write t ghel t ghel 0 ?? 0 ?? 0 ?? ns ce setup time t elwl t cs 0 ?? 0 ?? 0 ?? ns we setup time t wlel t ws 0 ?? 0 ?? 0 ?? ns ce hold time t wheh t ch 0 ?? 0 ?? 0 ?? ns we hold time t ehwh t wh 0 ?? 0 ?? 0 ?? ns write pulse width t wlwh t wp 30 ?? 35 ?? 45 ?? ns ce pulse width t eleh t cp 30 ?? 35 ?? 45 ?? ns write pulse width high t whwl t wph 25 ?? 25 ?? 25 ?? ns ce pulse width high t ehel t cph 25 ?? 25 ?? 25 ?? ns programming operation byte t whwh1 t whwh1 ? 8 ? ? 8 ?? 8 ? m s word 16 ? 16 ?? 16 ? sector erase operation * 1 t whwh2 t whwh2 ? 1 ?? 1 ?? 1 ? s v cc setup time ? t vcs 50 ?? 50 ?? 50 ?? m s rise time to v id * 2 ? t vidr 500 ?? 500 ?? 500 ?? ns voltage transition time * 2 ? t vlht 4 ?? 4 ?? 4 ?? m s write pulse width * 2 ? t wpp 100 ?? 100 ?? 100 ?? m s oe setup time to we active * 2 ? t oesp 4 ?? 4 ?? 4 ?? m s ce setup time to we active * 2 ? t csp 4 ?? 4 ?? 4 ?? m s recover time from ry/by ? t rb 0 ?? 0 ?? 0 ?? ns reset pulse width ? t rp 500 ?? 500 ?? 500 ?? ns reset high level period before read ? t rh 200 ?? 200 ?? 200 ?? ns byte switching low to output high-z ? t flqz ?? 25 ?? 25 ?? 30 ns
MBM29LV800TE/be 60/70/90 31 (continued) *1: does not include the preprogramming time. *2: for sector protection operation. parameter symbol MBM29LV800TE/be unit 60 70 90 jedec standard min typ max min typ max min typ max byte switching high to output active ? t fhqv ?? 60 ?? 70 ?? 90 ns program/erase valid to ry/by delay ? t busy ?? 90 ?? 90 ?? 90 ns delay time from embedded output enable ? t eoe ?? 60 ?? 70 ?? 90 ns erase time-out time ? t tow 50 50 ?? 50 ?? m s erase suspend transition time ? t spd 20 ?? 20 ?? 20 m s
MBM29LV800TE/be 60/70/90 32 n erase and programming performance n tsop (1) , fbga, csop pin capacitance notes : test conditions t a = + 25 c, f = 1.0 mhz dq 15 /a -1 pin capacitance is stipulated by output capacitance. parameter limits unit comments min typ max sector erase time ? 110s excludes programming time prior to erasure byte programming time ? 8300 m s excludes system-level overhead word programming time ? 16 360 chip programming time ? 8.4 25 s excludes system-level overhead erase/program cycle 100,000 ?? cycle ? parameter symbol test setup typ max unit input capacitance c in v in = 07.59.5pf output capacitance c out v out = 0 8.0 10.0 pf control pin capacitance c in2 v in = 0 10.0 13.0 pf
MBM29LV800TE/be 60/70/90 33 n timing diagram ? key to switching waveforms waveform inputs outputs must be steady may change from h to l may change from l to h "h" or "l": any change permitted does not apply will be steady will change from h to l will change from l to h changing, state unknown center line is high- impedance "off" state address address stable high-z high-z ce oe we outputs outputs valid t rc t acc t oe t df t ce t oh t oeh read operation timing diagram
MBM29LV800TE/be 60/70/90 34 address ce reset outputs high-z outputs valid address stable t rc t acc t rh t rp t rh t ce t oh hardware reset/read operation timing diagram
MBM29LV800TE/be 60/70/90 35 address data ce oe we 3rd bus cycle data polling 555h pa a0h pd dq 7 d out d out pa t wc t as t ah t rc t ce t whwh1 t wph t wp t ghwl t ds t dh t df t oh t oe t cs t ch notes : pa is the address of the memory location to be programmed. pd is the data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycles sequence. these waveforms are for the 16 mode (the addresses differ from 8 mode). alternate we controlled program operation timing diagram
MBM29LV800TE/be 60/70/90 36 address data we oe ce 3rd bus cycle data polling 555h pa a0h pd dq 7 d out pa t wc t as t ah t whwh1 t cph t cp t ghel t ds t dh t ws t wh alternate ce controlled program operation timing diagram notes : pa is the address of the memory location to be programmed. pd is the data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycles sequence. these waveforms are for the 16 mode (the addresses differ from 8 mode) .
MBM29LV800TE/be 60/70/90 37 address data v cc ce oe we 555h 2aah 555h 555h 2aah sa* t wc t as t ah t cs t ghwl t ch t wp t ds t vcs t dh t wph aah 55h 80h aah 55h 10h/ 30h 10h for chip erase chip/sector erase operation timing diagram * : sa is the sector address for sector erase. addresses = 555h (word) for chip erase. note : these waveforms are for the 16 mode (the addresses differ from 8 mode) .
MBM29LV800TE/be 60/70/90 38 data polling during embedded algorithm operation timing diagram * : dq 7 = valid data (the device has completed the embedded operation) . t oeh t ch t oe t ce t df t busy t eoe t whwh1 or t whwh2 ce dq 7 dq 6 to dq 0 ry/by dq 7 dq 7 = valid data dq 6 to dq 0 = outputs flag dq 6 to dq 0 valid data oe we high-z high-z data data *
MBM29LV800TE/be 60/70/90 39 t oeh ce we t oes oe dq 6 t oe t dh data dq 7 to dq 0 dq 6 toggle dq 6 stop toggling dq 6 toggle dq 7 to dq 0 data valid * toggle bit i during embedded algorithm operation timing diagram * : dq 6 = stops toggling. (the device has completed the embedded operation.) dq 2 vs. dq 6 * : dq 2 is read from the erase-suspended sector. enter embedded erasing erase suspend erase resume enter erase suspend program erase suspend program erase complete erase erase suspend read erase suspend read erase dq 6 dq 2 * we toggle dq 2 and dq 6 with oe or ce
MBM29LV800TE/be 60/70/90 40 ry/by timing diagram during program/erase operation timing diagram ce ry/by we rising edge of the last we signal t busy entire programming or erase operations reset , ry/by timing diagram t rp t rb t ready ry/by we reset
MBM29LV800TE/be 60/70/90 41 timing diagram for word mode configuration t ce t fhqv t elfh a -1 data output (dq 7 to dq 0 ) data output (dq 14 to dq 0 ) dq 15 ce byte dq 14 to dq 0 dq 15 /a -1 t elfl t acc t flqz a -1 data outputs (dq 14 to dq 0 ) data outputs (dq 7 to dq 0 ) dq 15 ce byte dq 14 to dq 0 dq 15 /a -1 timing diagram for byte mode configuration t as t ah ce or we byte input valid falling edge of last write signal byte timing diagram for write operations
MBM29LV800TE/be 60/70/90 42 t wpp t vlht t vlht t oe t csp t oesp t vcs t vlht t vlht a 18 , a 17 , a 16 a 15 , a 14 , a 13 a 12 a 6 , a 0 a 1 a 9 v cc oe v id v ih v id v ih we ce data spax 01h spay sector protection timing diagram spax : sector address to be protected. spay : next sector address to be protected. note : a- 1 is v il on byte mode.
MBM29LV800TE/be 60/70/90 43 temporary sector unprotection timing diagram unprotection period t vlht t vlht t vcs t vlht t vidr program or erase command sequence v cc v id v ih we ry/by ce reset
MBM29LV800TE/be 60/70/90 44 extended sector protection timing diagram spax : sector address to be protected spay : next sector address to be protected time-out : time-out window = 150 m s (min) v cc we oe ce t wc t wc t vlht t vidr t vcs time-out spax spax spay t wp t oe 60h 01h 40h 60h 60h data address a 6 , a 0 a 1 v id v ih reset
MBM29LV800TE/be 60/70/90 45 n flow chart embedded program tm algorithm notes : the sequence is applied for 16 mode. the addresses differ from 8 mode. embedded algorithm 555h/aah 555h/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data ? data polling program command sequence (address/command) : write program command sequence (see below) start no no yes yes embedded program algorithm in progress
MBM29LV800TE/be 60/70/90 46 embedded erase tm algorithm notes : the sequence is applied for 16 mode. the addresses differ from 8 mode. embedded algorithm 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah sector address /30h sector address /30h sector address /30h 2aah/55h erasure completed data = ffh ? data polling write erase command sequence (see below) start no yes embedded erase algorithm in progress chip erase command sequence (address/command) : individual sector/multiple sector erase command sequence (address/command) : additional sector erase commands are optional.
MBM29LV800TE/be 60/70/90 47 data polling algorithm * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = address for programming = any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. dq 7 = data? dq 5 = 1? fail pass dq 7 = data? * read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va start no no no yes yes yes
MBM29LV800TE/be 60/70/90 48 toggle bit algorithm *1 : read toggle bit twice to determine whether it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to 1. dq 6 = toggle? dq 5 = 1? dq 6 = toggle? read dq 7 to dq 0 addr. = v ih or v il read dq 7 to dq 0 addr. = v ih or v il read dq 7 to dq 0 addr. = v ih or v il start no no no yes yes yes *1 *1, *2 program/erase operation not complete.write reset command program/erase operation complete read dq 7 to dq 0 addr. = v ih or v il
MBM29LV800TE/be 60/70/90 49 start no no no yes yes yes data = 01h? device failed plscnt = 25? plscnt = 1 remove v id from a 9 write reset command remove v id from a 9 write reset command sector protection completed protect another sector ? increment plscnt read from sector address addr. = spa, a 1 = v ih a 6 = a 0 = v il setup sector addr. a 18 , a 17 ,a 16 , a 15 , a 14 , a 13 , a 12 oe = v id , a 9 = v id ce = v il , reset = v ih a 6 = a 0 = v il , a 1 = v ih activate we pulse time out 100 m s we = v ih , ce = oe = v il (a 9 should remain v id ) () () * sector protection algorithm * : a- 1 is v il on byte mode.
MBM29LV800TE/be 60/70/90 50 start perform erase or program operations reset = v id *1 reset = v ih temporary sector unprotection completed *2 temporary sector unprotection algorithm *1 : all protected sectors are unprotected. *2 : all previously protected sectors are protected once again.
MBM29LV800TE/be 60/70/90 51 start no yes yes data = 01h? plscnt = 1 no no yes device failed plscnt = 25? remove v id from reset write reset command sector protection completed protect other group ? increment plscnt read from sector address (addr. = spa, a 0 = v il , a 1 = v ih , a 6 = v il ) remove v id from reset write reset command time out 150 m s reset = v id wait to 4 m s no yes setup next sector address device is operating in temporary sector unprotection mode to protect secter write 60h to secter address (a 6 = a 0 = v il , a 1 = v ih ) to verify sector protection write 40h to secter address (a 6 = a 0 = v il , a 1 = v ih ) to setup sector protection write xxxh/60h extended sector protection entry? extended sector protection algorithm
MBM29LV800TE/be 60/70/90 52 555h/aah 555h/20h xxxh/90h xxxh/f0h xxxh/a0h 2aah/55h program address/program data programming completed last address? increment address verify data? data polling start no no yes yes set fast mode in fast program reset fast mode embedded programming algorithm for fast mode notes : the sequence is applied for 16 mode. the addresses differ from 8 mode. fast mode algorithm
MBM29LV800TE/be 60/70/90 53 n ordering information part no. package access time (ns) remarks MBM29LV800TE60tn MBM29LV800TE70tn MBM29LV800TE90tn 48-pin plastic tsop (1) (fpt-48p-m19) (normal bend) 60 70 90 top sector MBM29LV800TE60pcv MBM29LV800TE70pcv MBM29LV800TE90pcv 48-pin plastic csop (lcc-48p-m03) 60 70 90 MBM29LV800TE60pbt MBM29LV800TE70pbt MBM29LV800TE90pbt 48-ball plastic fbga (bga-48p-m20) 60 70 90 mbm29lv800be60tn mbm29lv800be70tn mbm29lv800be90tn 48-pin plastic tsop (1) (fpt-48p-m19) (normal bend) 60 70 90 bottom sector mbm29lv800be60pcv mbm29lv800be70pcv mbm29lv800be90pcv 48-pin plastic csop (lcc-48p-m03) 60 70 90 mbm29lv800be60pbt mbm29lv800be70pbt mbm29lv800be90pbt 48-ball plastic fbga (bga-48p-m20) 60 70 90 mbm29lv800 device number/description mbm29lv800 8 mega-bit (1 m 8-bit or 512 k 16-bit) cmos flash memory 3.0 v-only read, program, and erase package type tn = 48-pin thin small outline package (tsop) standard pinout pcv = 48-pin c-lead small outline package (csop) pbt = 48-ball fine pitch ball grid array package (fbga) t e 60 pcv speed option see product selector guide device revision boot code sector architecture t = top sector b = bottom sector
MBM29LV800TE/be 60/70/90 54 n package dimensions (continued) 48-pin plastic tsop (1) (fpt-48p-m19) note 1) * : values do not include resin protrusion. resin protrusion and gate protrusion are + 0.15 (.006) max (each side) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) . note : the values in parentheses are reference values. C .003 +.001 C 0.08 +0.03 .007 0.17 "a" (stand off height) 0.10(.004) (mounting height) (.472 .008) 12.00 0.20 lead no. 48 25 24 1 (.004 .002) 0.10(.004) m 1.10 +0.10 C 0.05 +.004 C .002 .043 0.10 0.05 (.009 .002) 0.22 0.05 (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2003 fujitsu limited f48029s-c-6-7 c 0~8 ? 0.25(.010) 0.50(.020) 0.60 0.15 (.024 .006) details of "a" part * *
MBM29LV800TE/be 60/70/90 55 (continued) 48-pin plastic csop (lcc-48p-m03) note 1) *1 : resin protrusion. (each side : + 0.15 (.006) max) . note 2) *2 : these dimensions do not include resin protrusion. note 3) pins width includes plating thickness. note 4) pins width do not include tie bar cutting remainder. dimensions in mm (inches) . note : the values in parentheses are reference values. c 2003 fujitsu limited c48056s-c-2-2 10.000.10(.394.004) 0.08(.003) 9.20(.362)ref 1 24 25 48 index index 9.500.10 (.374.004) 10.000.20 (.394.008) "a" 0.220.035 (.009.001) .002 C.0 +.002 C0 +0.05 0.05 0.950.05(.037.002) (mounting height) (stand off) 0.65(.026) 1.15(.045) details of "a" part 0?~10? lead no. * 2 * 1 0.40(.016)
MBM29LV800TE/be 60/70/90 56 (continued) 48-ball plastic fbga (bga-48p-m20) dimensions in mm (inches) . note : the values in parentheses are reference values. c 2003 fujitsu limited b48020s-c-2-2 8.00 0.20(.315 .008) 0.38 0.10(.015 .004) (stand off) (mounting height) 6.00 0.20 (.236 .008) 0.10(.004) 0.80(.031)typ 5.60(.220) 4.00(.157) 48- ? 0.45 0.05 (48- ? .018 .002) m ? 0.08(.003) h g fed c ba 6 5 4 3 2 1 .043 C .005 +.003 C 0.13 +0.12 1.08 (index area)
MBM29LV800TE/be 60/70/90 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0405 ? fujitsu limited printed in japan

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